1. Field of the Invention
The present invention relates to a film thickness prediction method, and a layout design method, a mask pattern design method of exposure mask, and a fabrication method of semiconductor integrated circuit to which the film thickness prediction method is applied.
2. Background Art
One of technologies for addressing higher integration of semiconductor integrated circuits, planarization processing is performed at fabrication of semiconductor integrated circuits. One of such planarization processing technologies, a chemical mechanical polishing method (hereinafter, may be referred to as “CMP method”) may be cited. FIG. 13 is a conceptual diagram of a polishing apparatus used in the CMP method. This polishing apparatus includes a polishing plate, a substrate holding stage, and a polishing agent slurry supply system. The polishing plate is supported by a rotational shaft of the rotating polishing plate and a polishing pad is provided on the surface thereof. The substrate holding stage is located above the polishing plate and supported by a substrate holding stage rotational shaft. For example, when the substrate is polished, the substrate is mounted on the substrate holding stage. The substrate holding stage rotational shaft is attached to a polishing pressure adjustment mechanism (not shown) for pressing the substrate holding stage toward the polishing pad. Further, the polishing plate is rotated while polishing agent slurry containing the polishing agent is supplied from the polishing agent slurry supply system to the polishing pad. Concurrently, while the substrate mounted on the substrate holding stage is rotated, the polishing pressure adjustment mechanism adjusts polishing pressure of the substrate against the polishing pad. In this way, the surface of the substrate can be polished.
When a thin film is formed on a circuit pattern and the thin film is planarized, it is extremely important to predict a thickness of the planarized thin film in advance for early solution to problems in semiconductor device manufacture and reduction in manufacturing cost. Further, in view of a characteristic analysis of semiconductor device, i.e., timing closure of integrated circuit, especially, in RC extraction, information on a sectional structure of semiconductor device is used. For this, it is necessary to predict a value of the film thickness of a thin film formed on a circuit pattern and to be planarized.
As a basic theory relating to polishing, there is Preston's law. This law is based on the assumption that a polishing rate is proportional to an amount of planarization work (amount of friction work) per unit area and time. Given that a relative velocity of a surface to be polished of a substrate and a polishing plate is v, pressure is P (constant regardless of polishing time t during polishing), and a remaining height of the surface of a thin film to be polished is X, the polishing rate can be expressed by the following equation (A), where “c” is a constant.−dX/dt=c·v·P  (A)
For example, Japanese Patent No. 3580036 discloses a simulation method when a substrate is sandwiched between a polishing head and a polishing cloth and projections and depressions formed on the substrate are polished. In the simulation method, a function expressing the height of the projections and depressions after a polishing time is elapsed with pressure applied by the polishing head to the substrate, a relative velocity between the polishing cloth and the substrate, an initial level difference between projections and depressions, the polishing time, Young's modulus of the polishing cloth, a thickness of the polishing cloth, and a density distribution of projections and depressions in a predetermined location on the substrate as parameters and an independent parameter of the pressure for the density distribution of projections and depressions is obtained in advance. For obtaining the height of the projections and depressions after a predetermined polishing time is elapsed, the pressure, the relative velocity, the initial level difference, the polishing time, the Young's modulus, the thickness of the polishing cloth, and the density distribution of projections and depressions are substituted into the function, and the final height of the projections and depressions after the polishing time is elapsed is directly obtained.
Further, for example, Japanese Patent No. 3743120 discloses a method of fabricating a semiconductor integrated circuit by forming a pattern on a first processed layer formed on a substrate, then forming a second processed layer on an entire surface, and planarizing the second processed layer by a chemical mechanical polishing method. In the method of fabricating a semiconductor integrated circuit, a mask pattern to be formed on an exposure mask used for pattern formation is designed according to a design method of the mask pattern including the steps of:
(i) segmenting the mask pattern into grid-like meshes having a predetermined size and obtaining a pattern area ratio αij in each mesh (i,j);
(ii) obtaining a pattern area ratio average value β(i,j) within a predetermined region centered around the mesh (i,j) of the mask pattern; and
(iii) providing a dummy pattern in the mesh (i,j) in which the pattern area ratio average value β(i,j) is less than a prescribed value, and
the pattern is formed on the first processed layer using the exposure mask fabricated according to the design method.